In the era of technological advancement, the liquid crystal display has been widely used to electronic display devices, such as television, computer, cell phone, personal digital assistant, etc. The liquid crystal display comprises source driver, gate driver, liquid crystal display panel, etc. The liquid crystal display panel includes pixel array; and the gate driver is used for sequentially turning on the corresponding pixel lines in the pixel array so as to transmit pixel data outputted by the source driver to the pixel, thereby to display an image to be displayed.
At present, the gate driver is generally formed on the array substrate of the liquid crystal display by array process, that is, the gate driver on array (GOA) process. This integrated process not only saves cost, but also can do beautiful design for bilaterally symmetrical liquid crystal panel; at the same time; this process saves the wiring space of the bonding area of the gate Integrated Circuit and the Fan-out area, thereby realizing a narrow border design; and this integrated process saves the Bonding process in the direction of the gate scanning line as well thus promoting the capability of producing and defect rate.
The gate driver usually consists of a plurality of shift registers in a cascade connection, and it lets the driving signal output terminal of each of the shift register correspond to a gate line separately so as to output scanning signals to all gate lines sequentially along the scanning direction. Structure of the specific shift register is shown in FIG. 1, comprising: an input unit 1, a reset unit 2, a node control unit 3, a pull-up unit 4, a pull-down unit 5, an input signal terminal Input, a reset signal terminal Reset, a first clock signal terminal ck and a reference signal terminal Vref. Wherein an output terminal of the input unit 1, an output terminal of the reset unit 2, a first terminal of the node control unit 3 and a control terminal of the pull-up unit 4 are all connected to a first node PU; both a second terminal of the node control unit 3 and a control terminal of the pull-down unit 5 are connected to a second node PD; both an output terminal of the pull-up unit 4 and an output terminal of the pull-down unit 5 are connected to a driving signal output terminal Out shifted on the register; the input unit 1 is configured to control the potential of the first node PU under the control of the input signal terminal Input, the reset unit 2 is configured to control the potential of the first node PU under the control of the reset signal terminal Reset, the node control unit 3 is configured to control the potential of the first node PU and the second node PD, the pull-up unit 4 is configured to provide signal of a first clock signal terminal CK for the driving signal output terminal Out under the control of the first node PU, and the pull-down unit 5 is configured to provide signal of a reference signal terminal Vref for the driving signal output terminal Out under the control of the second node PD.
At present, the shift register in the gate driver of the display panel is generally as shown in FIG. 1, the display panel outputs scanning signal to each gate line sequentially through the shift register of each stage along the scanning direction. However, with the higher resolution rate of display products, the power consumption of the display panel is increasing, which leads to great reduction of the standby time. Therefore, how to reduce the power consumption of display products to increase standby time is the technical problem that have to be solved by those skilled in the art.